1. Field of the Invention
The present invention relates to an electrically word-erasable non-volatile memory device, and to the biasing method thereof. In particular, the invention relates to a flash memory device.
2. Description of the Related Art
As is known, generally flash memories can be erased only by sectors, typically 512-Kbit sectors, while they can be programmed with a granularity that arrives at the single bit. In other flash memories it is possible to carry out erasing by pages that contain a certain number of words. Moreover, recently flash memories have been proposed that enable erasing of single words.
For example, in EP-A-1178491, a flash memory is described, in which the memory cells, instead of being formed in a single doped semiconductor region, normally of P-type for N-channel memory cells, are formed in a plurality of P-wells, in turn accommodated in an N-type well. See, in this connection, FIGS. 1 and 2, which illustrate the simplified diagram and a cross-section through a portion of a memory device described in EP-A-1 178 491. In these figures, a substrate 1 of P-type accommodates an N-type well 2, in turn accommodating a plurality of P-wells 3.
As may be noted in particular in FIG. 1, the P-wells 3 have the shape of vertical strips that extend alongside one another in a direction transverse to the rows. Source regions 4 and drain regions 5 are formed within the P-wells 3 (FIG. 2).
The memory columns are connected to bitlines BL grouped in packets CP, one for each P-well (FIG. 1). Then, memory cells arranged on a same row (and hence connected to a same wordline WL) are divided into a plurality of subsets, each subset being made up of the memory cells formed in a same P-well 3. In this type of architecture, the memory cells that are arranged on a same row and are provided in a same P-well form a single word.
Thereby, it is possible to word-erase the memory, selecting just one of the P-wells and applying a high negative voltage to the wordline to which the word to be erased is connected.
In the document cited, it is moreover proposed to provide a plurality of “physical sectors”, each accommodated in an own N-well. The overall architecture is not, however, described precisely. Each “physical sector” is equipped with its own reading and programming circuits (sense amplifiers and program loads), so that the structure as a whole requires quite a lot of space, and it is not indicated how to manage the different “physical sectors” during erasing of a word so as to prevent problems of undesirable erasing or stresses on the non-selected sectors. Furthermore, to eliminate the stress induced in memory word cells that are not to be erased but are provided in the same “physical sector” as the word to be erased, a complex refreshing mechanism is proposed.